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Using Power Management Controller Drivers to Debug Low Power Platform States

BY Rajneesh Bhardwaj ON Jun 12, 2019
This post describes how to use the power management controller (PMC) core driver and telemetry driver to debug low power platform states, such as S0ix. 

Basic Concepts

On a typical Intel chipset, the power management controller (PMC) is responsible for platform-wide power management. On Intel® Core™ processors, it is present on the Platform Controller Hub (PCH) and on Intel Atom® SoCs, it is present on the South Complex Unit (SCU). PMC is responsible for platform-wide power management during active and idle times. It determines the package C-states based on the system idleness and latency tolerance reporting by various IP blocks on the PCH and on the North Complex. PMC communicates periodically with another power management entity present on the North Complex, known as PUNIT, as well as on an “as-needed” basis to apply comprehensive platform power management policies.
PMC is also responsible for enhanced low power states like S0ix. Based on various factors, the PMC determines whether the platform can enter a low power idle state and asserts a signal known as SLP_S0#. From the Linux* Kernel standpoint, the suspend to idle flow should generally take us to package c10 and eventually to S0ix. 

PMC Driver for Intel Core Processors

The driver (intel_pmc_core.c) is the Kernel gateway to the PMC hardware for Intel Core processors. (This driver is not applicable for Intel Atom SoC, which uses another set of drivers.) The PMC driver provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix.

Supported platforms include:

  1. Intel® microarchitecture code name Skylake
  2. Intel® microarchitecture code name Kaby Lake
  3. Intel® microarchitecture code name Cannon Lake
  4. Intel® microarchitecture code name Coffee Lake
  5. Intel® microarchitecture code name Ice Lake

 

Supported features include:

  • PCH IP power gating status
  • S0ix Residency Counter
  • HSIO/MPHY Lanes power gating status (see Note)
  • PLL Status (see Note)
  • LTR Show
  • LTR Ignore
  • SLP_S0_DEBUG (see Note)
  • Package C-state Counters

Note: This feature is not supported on all platforms.

Attributes

The PMC Core driver creates its debugfs attributes under the /sys/kernel/debug/pmc_core directory.

PCH IP power gating status (pch_ip_power_gating_status)

This reads the power gating status of various devices present on the PCH and is intended to be used for debugging purposes, while tuning the platform for power optimizations. It also helps understand which devices (on PCH) are blocking the system from entering a low power state.

Further documentation can be found in the 7th Generation Intel Processor Families for U/Y Platforms, Datasheet Volume 2.

Sample output (stripped and not in order):

cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status PMC       State: Not Power gated
OPI-DMI State: Not Power gated
XHCI    State: Power gated
LPSS    State: Power gated

S0ix Residency Counter (slp_s0_residency_usec)

The SLP_S0_RESIDENCY counter increments in one step at every 100us when the SLP_S0# signal is asserted, that is, when the platform is in S0ix state. This attribute identifies whether the platform entered S0ix or not, and  also calculates the percentage residency in that state for a given time window.

HSIO/MPHY Lanes power gating status (mphy_lanes_power_gating_status)

The PCH implements a number of High Speed I/O (HSIO) lanes split between PCIe*, USB 3.0, SATA, GbE, USB OTG, and SSIC. This attribute shows the current power gating status of the available ModPhy Core lanes by sending a Message To the PMC (MTPMC) that contains the XRAM register offset for the MPHY_CORE_STS_0 and MPHY_CORE_STS_1, and then reading the response Message From the PMC (MFPMC).

Note: This feature requires the PMC_READ_DISABLE setting to be disabled in the platform BIOS and is only supported on the Sunrisepoint PCH (part of Skylake) and Kaby Lake based platforms.

PLL Status (pll_status)

ModPhy Common lanes can provide the clock gating status for the important system PLLs such as Gen2 USB3PCIE2 PLL, DMIPCIE3 PLL, SATA PLL, and MIPI PLL. PLL idling is a must before the system can enter the S0ix state.

Note: This feature is based on the MTPMC-MFPMC interface and requires the PMC_READ_DISABLE bit to be disabled in BIOS. It is available only for the Sunrisepoint PCH (part of Skylake).

LTR Show (ltr_show)

This attribute is used to show the Latency Tolerance Reporting (LTR) for IPs on the PCH as reported by the PMC. The PMC reports the aggregated LTR to the PUNIT, which then uses this information while selecting a particular package C-state. Both Snoop and Non Snoop LTR (decoded) are shown with this attribute.

LTR Ignore (ltr_ignore)

When a particular IP Offset bit is set, the PMC ignores the LTR value reported by the corresponding IP when the PMC performs the latency coalescing. This feature helps when debugging why deeper package C-states are not working for a platform. It is also useful for S0ix debug when S0ix is blocked due to bad LTR.

Usage:  

echo <IP Offset> > /sys/kernel/debug/pmc_core/ltr_ignore

Use the following table for performing the LTR Ignore operation:

IP Offset IP Name
0 SPA
1 SPB
2 SATA
3 GBE
4 XHCI
5 RSVD
6 ME
7 EVA
8 SPC
9 Azalia/ADSP
10 RSVD
11 LPSS
12 SPD
13 SPE
14 Camera
15 ESPI
16 SCC
17 ISH
18 UFSX2*
19 EMMC*
20 WIGIG**

 

Table Notes:

* Not applicable to Skylake and Kaby Lake.

** Ice Lake only.

SLP_S0_DEBUG (slp_s0_debug_status and slp_s0_dbg_latch)

This debug feature is available on Cannon Lake and beyond. The Cannon Lake PCH has special registers that can latch device pm states just before attempting S0ix. The trigger happens when package enters c10 or by writing 1 to the slp_s0_dbg_latch exclusively.

Usage:

echo 1 > slp_s0_dbg_latch
cat slp_s0_debug_status

Package C-state Counters (package_cstate_show)

This attribute prints the current count for all available package C-state MSRs. If a system is not able to reach package c10 during a suspend attempt, it cannot enter S0ix. Therefore, package c10 is a prerequisite for S0ix entry, assuming package c10 is the deepest package C-state on the given platform.

If package c10 is not working but package c8 is working, this typically indicates a problem with DMC firmware.

Telemetry Driver

The telemetry driver is exclusively used for the Intel Atom SoC and currently supports the Broxton family-based Apollo Lake and Gemini Lake platforms. The telemetry driver has a dependency on intel_pmc_ipc and intel_punit_ipc drivers, because the underlying PMC hardware architecture is different than Intel Core processors, where PMC provides a rich range of MMIO registers. (There are global config registers available on Intel Atom SoCs, but they are few and telemetry architecture is based mostly on event sampling.)

Usage:

cat /sys/kernel/debug/telemetry/pss_info
cat /sys/kernel/debug/telemetry/ioss_info
cat /sys/kernel/debug/telemetry/s0ix_residency_usec
cat /sys/kernel/debug/telemetry/soc_states
cat /sys/kernel/debug/telemetry/pss_trace_verbosity
cat /sys/kernel/debug/telemetry/ioss_trace_verbosity

This telemetry driver provides debug information about both North Complex or Primary Subsystem (PSS) and South Complex or IO Subsystem (IOSS) and includes the following attributes:

  • The pss_info and ioss_info attributes provide detailed information on power gating status for IPs on PSS and IOSS.
  • The pss_trace_verbosity and ioss_trace_verbosity attributes can be used to tune the tracing verbosity.
  • The s0ix_residency_usec attribute is used to show SLP_S0# residency for both deep and shallow S0ix states that exist on Intel Atom SoCs. (In a nutshell, it is similar to the slp_s0_residency_counter in the intel_pmc_core driver.)

Summary

This post has described how to use the power management controller (PMC) core driver and Telemetry driver to debug low power platform states, such as S0ix. Users can enable this driver by using the kernel config option INTEL_PMC_CORE.

This driver is available upstream and the latest code can be found at https://github.com/torvalds/linux/blob/master/drivers/platform/x86/intel_pmc_core.c

Useful Resources

Legal Disclaimers

Intel, Intel Atom, and Intel Core are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.