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Description

Cache Monitoring Technology (CMT), Memory Bandwidth Monitoring (MBM), Cache Allocation Technology (CAT), Code and Data Prioritization (CDP) and Memory Bandwidth Allocation Technology (MBA) are component features that make up Intel® Resource Director Technology (Intel® RDT). These components provide a hardware framework to monitor and control the utilization of shared processor resources, like last level cache and memory bandwidth. As multithreaded and multicore platform architectures continue to evolve, running workloads in single-threaded, multithreaded, or complex virtual machine environment, the last level cache and memory bandwidth are key resources to manage. Intel introduces CMT, MBM, CAT, CDP and MBA to manage these various workloads across shared resources.

 

CMT and MBM

CMT and MBM are features that allow privileged software (i.e. operating system or virtual machine monitor) to monitor and characterize the usage of cache and memory bandwidth by applications running on the platform. Use CMT and MBM to do the following:

  • To detect if the platform supports this monitoring capabilities (via CPUID).
  • For privileged software to assign an ID for each of applications or VMs that are scheduled to run on a core. This ID is called the Resource Monitoring ID (RMID).
  • To monitor cache occupancy and memory bandwidth on a per-RMID basis.
  • For an OS or VMM to read LLC occupancy and memory bandwidth for a given RMID at any time.

 

CAT, CDP and MBA

CAT, CDP and MBA are features that allow privileged software to control allocation of CPU’s shared last level cache and memory bandwidth. Once configured, the processor will allocate portions of cache and/or memory bandwidth according to the established class of service (COS or CLOS). The processor obeys the COS rules when it runs an application thread or application process. This can be accomplished by performing these steps:

  • Determine if the CPU supports the CAT, CDP and MBA feature (CPUID).
    • Supported CPU’s can be found here.
  • Configure the COS to define the amount of resources (cache space or memory bandwidth) available. This configuration is at the processor package level and is common to all logical processors.
  • Associate each logical processor with an available COS.
  • Run the application on the logical processor that uses the desired COS.
  • Note: this operation can also be done at task scheduler level where COS association is changed on schedule in and out operations per task/process basis.

 

Additional Intel® RDT Resources

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