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FPGA Partial Reconfiguration


The Partial Reconfiguration Design Flow is supported in the Intel Quartus Prime® Pro Edition software for Intel Arria 10 Devices with the following key features:
  • Command line and graphical user interface for compilation and analysis
  • Hierarchical Partial Reconfiguration that allows you to create child PR partitions in your design
  • Simulation of Partial Reconfiguration that allows you to observe the resulting change and the intermediate effect in a reconfiguration partition
  • Signal Tap debug with simultaneous acquisition of both the Static region and Partial Reconfiguration regions
  • Quartus Prime documentation for Creating a Partial Reconfiguration Design is available in the Quartus Prime Pro Edition Handbook Volume 1
  • Refer to the Partial Reconfiguration Solutions IP User Guide for information about the Intel FPGA Partial Reconfiguration IP cores


Partial reconfiguration improves effective logic density by removing the need to place in the FPGA functions that do not operate simultaneously. Instead, you can store these functions in external memory and load them as needed. This operation reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and cost, and reducing power consumption.


The fpga-partial-reconfig gitub repository contains scripts, tutorials, and reference designs for the Intel FPGA PR design flow. The repository is available here:


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