Chapter 4. drm/i915 Intel GFX Driver

Table of Contents

Core Driver Infrastructure
Runtime Power Management
Interrupt Handling
Intel GVT-g Guest Support(vGPU)
Display Hardware Handling
Mode Setting Infrastructure
Frontbuffer Tracking
Display FIFO Underrun Reporting
Plane Configuration
Atomic Plane Helpers
Output Probing
High Definition Audio
Panel Self Refresh PSR (PSR/SRD)
Frame Buffer Compression (FBC)
Display Refresh Rate Switching (DRRS)
CSR firmware support for DMC
Video BIOS Table (VBT)
Memory Management and Command Submission
Batchbuffer Parsing
Batchbuffer Pools
Logical Rings, Logical Ring Contexts and Execlists
Global GTT views
GTT Fences and Swizzling
Object Tiling IOCTLs
Buffer Object Eviction
Buffer Object Memory Shrinking
GuC-specific firmware loader
GuC-based command submission
GuC Firmware Layout
i915_ppgtt_create and i915_ppgtt_release
i915_context_create and i915_context_free

The drm/i915 driver supports all (with the exception of some very early models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver.

Core Driver Infrastructure

This section covers core driver infrastructure used by both the display and the GEM parts of the driver.

Runtime Power Management

__intel_display_power_is_enabled — unlocked check for a power domain
intel_display_power_is_enabled — check for a power domain
intel_display_set_init_power — set the initial power domain state
intel_display_power_get — grab a power domain reference
intel_display_power_get_if_enabled — grab a reference for an enabled display power domain
intel_display_power_put — release a power domain reference
intel_power_domains_init — initializes the power domain structures
intel_power_domains_fini — finalizes the power domain structures
intel_power_domains_init_hw — initialize hardware power domain state
intel_power_domains_suspend — suspend power domain state
intel_runtime_pm_get — grab a runtime pm reference
intel_runtime_pm_get_if_in_use — grab a runtime pm reference if device in use
intel_runtime_pm_get_noresume — grab a runtime pm reference
intel_runtime_pm_put — release a runtime pm reference
intel_runtime_pm_enable — enable runtime pm
intel_uncore_forcewake_get — grab forcewake domain references
intel_uncore_forcewake_get__locked — grab forcewake domain references
intel_uncore_forcewake_put — release a forcewake domain reference
intel_uncore_forcewake_put__locked — grab forcewake domain references
gen6_reset_engines — reset individual engines
intel_uncore_forcewake_for_reg — which forcewake domains are needed to access a register

The i915 driver supports dynamic enabling and disabling of entire hardware blocks at runtime. This is especially important on the display side where software is supposed to control many power gates manually on recent hardware, since on the GT side a lot of the power management is done by the hardware. But even there some manual control at the device level is required.

Since i915 supports a diverse set of platforms with a unified codebase and hardware engineers just love to shuffle functionality around between power domains there's a sizeable amount of indirection required. This file provides generic functions to the driver for grabbing and releasing references for abstract power domains. It then maps those to the actual power wells present for a given platform.

Interrupt Handling

intel_irq_init — initializes irq support
intel_runtime_pm_disable_interrupts — runtime interrupt disabling
intel_runtime_pm_enable_interrupts — runtime interrupt enabling

These functions provide the basic support for enabling and disabling the interrupt handling support. There's a lot more functionality in i915_irq.c and related files, but that will be described in separate chapters.

Intel GVT-g Guest Support(vGPU)

i915_check_vgpu — detect virtual GPU
intel_vgt_deballoon — deballoon reserved graphics address trunks
intel_vgt_balloon — balloon out reserved graphics address trunks

Intel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine. This file provides vGPU specific optimizations when running in a virtual machine, to reduce the complexity of vGPU emulation and to improve the overall performance.

A primary function introduced here is so-called address space ballooning technique. Intel GVT-g partitions global graphics memory among multiple VMs, so each VM can directly access a portion of the memory without hypervisor's intervention, e.g. filling textures or queuing commands. However with the partitioning an unmodified i915 driver would assume a smaller graphics memory starting from address ZERO, then requires vGPU emulation module to translate the graphics address between 'guest view' and 'host view', for all registers and command opcodes which contain a graphics memory address. To reduce the complexity, Intel GVT-g introduces address space ballooning, by telling the exact partitioning knowledge to each guest i915 driver, which then reserves and prevents non-allocated portions from allocation. Thus vGPU emulation module only needs to scan and validate graphics addresses without complexity of address translation.