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Description

Cache Monitoring Technology (CMT), Memory Bandwidth Monitoring (MBM), Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) Technology provide the hardware framework to monitor and control the utilization of shared resources, like last level cache, memory bandwidth. As multithreaded and multicore platform architectures emerge, running workloads in single-threaded, multithreaded, or complex virtual machine environment, the last level cache and memory bandwidth are key resources to manage. Intel introduces CMT, MBM, CAT and CDP to manage these various workloads across shared resources. 

 

CMT and MBM

CMT and MBM are new features that allows an operating system (OS) or Hypervisor/virtual machine monitor (VMM) to determine the usage of cache and memory bandwidth by applications running on the platform. Use CMT and MBM to do the following:

  • To detect if the platform supports this monitoring capabilities (via CPUID).  
  • For an OS or VMM to assign an ID for each of applications or VMs that are scheduled to run on a core. This ID is called the Resource Monitoring ID (RMID).      
  • To monitor cache occupancy and memory bandwidth on a per-RMID basis.
  • For an OS or VMM to read LLC occupancy and memory bandwidth for a given RMID at any time.  

 

CAT and CDP

CAT and CDP are new features that allows an OS or Hypervisor/VMM to control allocation of CPU’s shared last level cache. Once CAT or CDP is configured, the processor allows access to portions of the cache according to the established class of service (COS). The processor obeys the COS rules when it runs an application thread or application process. This can be accomplished by performing these steps:

  • Determine if the CPU supports the CAT and CDP feature.
    • The CAT is supported on the following 6 SKUs for Intel(R) Xeon(R) processor E5 v3 family: E5-2658 v3, E5-2658A v3, E5-2648L v3, E5-2628L v3, E5-2618L v3, and E5-2608L v3 and all Intel(R) Xeon(R) processor D SKUs.
  • Configure the COS to define the amount of resources (cache space) available. This configuration is at the processor level and is common to all logical processors.
  • Associate each logical processor with an available COS.

Run the application on the logical processor that uses the desired COS

 

About CMT, MBM, CAT and CDP software package:

This software package provides basic support for Cache Monitoring Technology (CMT), Memory Bandwidth Monitoring (MBM), Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) Technology. This release supports last level cache occupancy monitoring on a per core or logical thread basis as well as scheduler-integrated perf (Kernel Version 4. 1 or onwards) last level cache occupancy monitoring per application PID (and all associated TIDs) basis. The memory bandwidth monitoring on a per core or logical thread basis only. MBM supports two types of events reporting local and remote memory bandwidth. Both events are reported on a per core or logical thread basis. Local memory bandwidth reports the bandwidth of a thread accessing memory associated with the local socket. In a dual socket system, the remote memory bandwidth reports the bandwidth of a thread accessing the remote socket. The monitoring utility does not track application migration across cores when static monitoring approach is used. Instead, applications should be pinned to cores to track last level cache occupancy and memory bandwidth. The monitoring utility associates a Resource Monitoring ID (RMID) per core or logical thread for static assignment approach when it initially comes up. The command line utility provides the necessary functionality to set up the CAT and CDP capabilities. The software provides flags to configure the class of service (CLOS) and associate cores / logical threads with a class of service. The Intel(R) Xeon(R) processor E5 v3 generation supports four classes of service and a set of pre-defined classes of service that should not be changed at run time. Intel(R) Xeon(R) processor D generation supports sixteen classes of service. There are no pre-defined classes of service and they can be changed at run time. Intel(R) Xeon(R) processor E5 v3 and Intel(R) Xeon(R) processor D generations supports Core/Logical thread association with a class of service can be changed dynamically. CMT is supported on all Intel(R) Xeon(R) processor E5 v3 and Intel(R) Xeon(R) processor D SKUs. CAT is supported on the following 6 SKUs for Intel(R) Xeon(R) processor E5 v3 family: E5-2658 v3, E5-2658A v3, E5-2648L v3, E5-2628L v3, E5-2618L v3, and E5-2608L v3 and all Intel(R) Xeon(R) processor D SKUs. Use of concurrent monitoring instances is possible as long as each instance monitors exclusive set of cores. Library APIs are also thread safe.

For additional CMT, MBM, CAT and CDP details please see refer to the Intel(R) Architecture Software Development Manuals available at: http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html Specific information with regard to CMT, MBM, CAT and CDP can be found in Chapter 17.14 and 17.15.

GIT

The development of CMT, MBM, CAT and CDP is hosted on GitHub repository:

Note: At current project stage we are not using any of the integrate, merge or tracking features of GitHub.

 

The latest CMT, MBM, CAT and CDP software package can be found below:

Maintainers

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